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<div class="header">
  <div class="headertitle"><div class="title">ADC (Analog Digital Converter)<div class="ingroups"><a class="el" href="group__group__hal__impl.html">CAT1 Implementation Specific</a></div></div></div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<h1><a class="anchor" id="cyhal_adc_impl_features"></a>
Features</h1>
<p >The CAT1A/CAT2 (PMG/PSoC™ 4/PSoC™ 6/XMC7™) ADC supports the following features:</p><ul>
<li>Resolution: 12 bit</li>
<li>Only <a class="el" href="group__group__hal__general__types.html#gga246fde0e79029f514ce3846b31e366d7a6f0f4df45e9cac012a2c8e5ba736241b">CYHAL_POWER_LEVEL_DEFAULT</a> and CYHAL_POWER_LEVEL_OFF are defined. The default power level will automatically adjust based on smple rate.</li>
<li>Average counts: 2, 4, 8, 16, 32, 64, 128, 256</li>
</ul>
<p >CAT1A supports DMA-based transfer when using <a class="el" href="group__group__hal__adc.html#ga7386fc156403ea08380c4410665b4ae2">cyhal_adc_read_async</a>. When using <a class="el" href="group__group__hal__adc.html#ga4bdd118986c58fdfe4d832123fb8a31d">cyhal_adc_read_async_uv</a>, only interrupt-driven software copy is supported.</p>
<p >CAT1A/CAT2 support the following features:</p><ul>
<li>Up to four unique acquisition times</li>
</ul>
<p >CAT1C supports the following features:</p><ul>
<li>Unique acquisition time per channel</li>
<li>Single-ended channels only, referenced to VREF</li>
<li>Internal VREF only</li>
<li>No external bypass</li>
</ul>
<p >After initializing the ADC or changing the reference or bypass selection, it may be necessary to wait up to 210 us for the reference buffer to settle. See the architecture TRM (Analog Subsystem -&gt; SAR ADC -&gt; Architecture -&gt; SARREF) for device specific guidance.</p>
<dl class="section note"><dt>Note</dt><dd>On CAT1C devices, the <a class="el" href="group__group__hal__types__implementation.html#gae6e4ea4100036d96d2efc006a3f69c9b">cyhal_source_t</a> object populated by <a class="el" href="group__group__hal__adc.html#ga0773c23aa717891206dfba927b99d38a">cyhal_adc_enable_output</a> is only valid as long as the last channel initialized is not disabled, and no new channels are added. If it necessary to make any of these changes, disable the output using <a class="el" href="group__group__hal__adc.html#gabfb66a94f69b8d5c27da8dbe324e6a82">cyhal_adc_disable_output</a>, then re-enable </dd></dl>
<table class="memberdecls">
<tr class="memitem:ga722f74fbfc67ef6842b9d3b1a7971c73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__impl__adc.html#ga722f74fbfc67ef6842b9d3b1a7971c73">CYHAL_ADC_AVG_MODE_SEQUENTIAL</a>&#160;&#160;&#160;(1u &lt;&lt; (<a class="el" href="group__group__hal__adc.html#gaf5c909ab5cc7409a896abceda7da5773">CYHAL_ADC_AVG_MODE_MAX_SHIFT</a> + 1u))</td></tr>
<tr class="memdesc:ga722f74fbfc67ef6842b9d3b1a7971c73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Convert all samples to be averaged back to back, before proceeding to the next channel.  <a href="group__group__hal__impl__adc.html#ga722f74fbfc67ef6842b9d3b1a7971c73">More...</a><br /></td></tr>
<tr class="separator:ga722f74fbfc67ef6842b9d3b1a7971c73"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga722f74fbfc67ef6842b9d3b1a7971c73" name="ga722f74fbfc67ef6842b9d3b1a7971c73"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga722f74fbfc67ef6842b9d3b1a7971c73">&#9670;&nbsp;</a></span>CYHAL_ADC_AVG_MODE_SEQUENTIAL</h2>

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          <td class="memname">#define CYHAL_ADC_AVG_MODE_SEQUENTIAL&#160;&#160;&#160;(1u &lt;&lt; (<a class="el" href="group__group__hal__adc.html#gaf5c909ab5cc7409a896abceda7da5773">CYHAL_ADC_AVG_MODE_MAX_SHIFT</a> + 1u))</td>
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<p>Convert all samples to be averaged back to back, before proceeding to the next channel. </p>
<h1><a class="anchor" id="group_hal_impl_adc_interconnect"></a>
Interconnect</h1>
<p >In PSoC™ each ADC has a single input trigger which, when activated, will initiate an ADC scan. Each ADC also has an output trigger which will be activated when a scan is completed. This is the default behavior. </p>

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